Traditional CMOS (complementary metal oxide semiconductor) techniques include process flows for constructing planar FET devices. With planar FETs, increased transistor density can be achieved by decreasing the pitch between transistor gate elements. However, with planar FET devices, the ability to decrease gate pitch is limited by the required gate length, spacer thickness, and source/drain size. In recent years, there has been significant research and development with regard to vertical FET devices, which decouple the gate length from the gate pitch requirement and enable scaling of transistor density. In general, vertical FET devices are designed to have gate structures that are formed on sidewalls of a vertical channel structure (e.g., a vertical semiconductor fin or vertical nanowire). Further, vertical FET devices include doped source/drain regions, wherein one doped source/drain region is formed on top of the vertical channel structure, and wherein another doped source/drain region is formed underneath the vertical channel structure. With vertical FET devices, scaling is determined by how closely conductive contacts to source and drain regions can be placed. With current state of the art technologies, vertical FET structures are suitable for technology nodes of 5 nm and beyond. In addition, the use of III-V compound semiconductor materials to form source/drain regions and vertical channel structures for vertical FET devices is highly desirable due to the increased electron mobility of III-V compound semiconductor materials.